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2020-202x lithographic processes at Intel, Samsung and TSMC

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As we have seen in other articles on this subject, the industry faces several challenges in the short and long term. The first of these is undoubtedly the decrease of the nanometer to obtain a higher inclination, a higher frequency and less or equal use, but after this there are some equal or more important if possible.

Transistors, the first step in a new eramicron-lab-wafer

Something we are already talking about and important for understanding this article, so we won't go too far here. FinFET time is coming to an end, mainly because of the way it is built and its three gates on the three sides of the transistor. Just as they are 3D transistors, the reduction of nanometers and the space between them is forcing the industry to leave them to reach the highest potential.

He already has a name and is producing: Gate All Around or GAA, also known as HNS in the use of vertical integrated nanoblades, is a new reality for this type of transistor.

TSMC-process-lead-Slides-20200427

In this new version the nanolayers are significantly reduced, developing nanowires and electrostatics, so the length of the gates is reduced from 16 nm in FFFET to 13 nm (or less) in the GAA, Connected to Poly Pitch (CPP)That is, a lower CPP equals a higher magnitude with pure logic.

In short, the problem here is that three big companies approach this at different times: TSMC won't cut it until, at least, its 3 nm, Samsung will have it in production at 5 nm and Intel has not given any details about it.

Reduction of pins per transistor to save space

TSMC-process-lead-Slides

The inclusion of leaves and their gates will have another direct effect as the nanometers continue to be reduced, and they are nothing more than a reduction of pies or wings. This has the direct effect of controlling the transistor's current transmission, since engineers are left with less space and options to carry out endless cycles and reduce leaks.

All of this is focused on cells, which is a fundamental part of understanding how GAAs will work. These cells are derived tracks (tracks), reduced by each lithographic jump to improve the intensity of individuals and themselves minimum iron concentration (MMP).

The small number of cells reduces the vertical and horizontal space, and because of this all the elements they make have to be reduced, making it difficult to use transistors.

TSMC-process-lead-Slides-2

So, the next step in the GAA (HNS) call CFET or Flementary FET. It is basically a general step in terms of population density as it shows the two most specific set of FETs: nFET and PFET.

The difference with the Nanoblades in the GAA is that two higher weights are given that as the cells are reduced, additional CFETs can be added to compensate, where Gates is now more focused and in this case more End the tone between each CFET.

Logically this has implications for resilience that still need to be studied, but is already being explored by the three main ones. We don't know what each launch will be or how they plan to solve problems such as connectivity (a special article on this topic soon), but first-rate improvements are sure to be the way to go (from 1, 4X to 2X for the best designs ).

Prospects for lithographic processes by 2020, 2021 and 2022

Intel, Samsung, TSMC 2019

Although it looks like the industry has some plans for the future, the reality is that they are as good as time goes. For this reason and to see all of the above and future articles, we have to assume that the future, today, is three years in length and has many questions that could influence some of the shortened reforms already mentioned.

What we are trying to say is that if this in itself almost runs the industry after pre-launch, we should understand that lithographic processes increase over time because the industry needs to work longer to solve the following challenges in order to keep going down nanometers.

This trend will definitely improve until 2030, when we are likely to break the atom and when we will face the next problem. At that time and looking back to having a clear start, in 2019 Intel released its 10nm, its Samsung 7nm LPP and its TSMC 7nm FF.

Here it should be noted that although Intel was leading itself through its lithographic process, this benefit was not as real as the high performance version was not available and therefore everything is such a superstition.

Intel, Samsung TSMC 2020

Although Intel has 10 nm of its population, this 2020 will not be the year it will pay off, in any sector, because the company aims to make it 10 nm ++ strong by 2021.

This year 2020 will all change drastically though 5nm TSMC With the truly amazing complexity of 185 million transmitors per mm2, the fact is that they will not be directly involved with high performance products like the one that took place at Intel in 2019.

Samsung for its part will be following TSMC in a much smaller but more profitable process. Intel without upgrading to a higher level with eyes on 2021.

To be effective during the speech process, it should be pointed out that even though companies confirm the graphs, the reality is that it will be really difficult to see products in the aforementioned lithographic processes. That is why in 2022 it is referred to as a potential year.

Intel, Samsung and TSMC 2022

Intel may have its 7nm by the end of 2021, but TSMC will probably not have 3FFs for that year, however they are heading to 2022, as they face problems that they must begin to solve.

Instead, Samsung could have 3 nm HNS by the end of that year and with the aim of making the final products in early 2022, when it can compete with Intel on a larger or smaller scale. In any case, the sector is changing dramatically, where development is likely to be delayed, so we will be looking to see changes in real-time for lithographic processes.

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