It was at Computex 2021 that AMD surprised everyone with the new announcement of its line of gaming processors for the end of 2021 to compete with Intel’s Alder Lake-S. The novelty is only one, but it will skyrocket the performance of the processors and give us one more clue about the design of the Zen 3. It will be. 3D V-Cache stack with TSMC at the helm.
AMD 3D V-Cache Stack, TSMC’s X3D implementation for Zen 3
Hope you enjoyed all the new technology we announced at #computex 2021. So proud of our @AMD Ryzen Desktop APU, @Radeon Mobile GPUs, FidelityFX Super Resolution and our brand new 3D chip technology – bringing the best in high performance computing !! pic.twitter.com/0memR0kPLu
– Lisa Su (@LisaSu) June 1, 2021
The company previously warned in 2018 that it was working on a new layered development model in true Intel Foveros style called the X3D, and since then we’ve only seen brushstrokes. At least until AMD pulled the canvas and showed nothing less than a prototype Ryzen 9 5900X with technology from vertical stacking for SRAM as L3 cache.
The data is partly concrete, but also partly concise and we will surely talk more about this technology in the future. But new is new and the data is starting to come out and it’s really interesting. On the one hand, AMD confirms that this technology 3D V-Cache stack
This excludes the new Milan server processors and the Threadripper, so AMD is looking to stand out in the sector where there is more competition today: in gaming or the master stream.
The processors are not yet in production, but are expected to arrive shortly with TSMC’s release no earlier than late 2021 or early 2022, oddly around the Alder Lake-S presentation and launch dates. At the same time, it shows that AMD will take at least 6 more months to launch Zen 4 as such.
On the other hand, it is curious how these statements neither affirm nor deny whether we will only see them on the desktop or this technology will be extended to monolithic matrix laptops as well, and by default it is not. not specified if they will reach the new APUs.
The physical limits of 3D V-Cache technology revealed
I’m trying to confirm that the TSV sites were clearly visible from the first chip shots we saw of a Zen 3 CCD.
– Andreas Schilling (@aschiling) June 1, 2021
What we also know for sure is that in said matrix, an SRAM stack will be interposed vertically as a cache of an exact size of 64MB in the form of L3, which, added to the 32MB that Ryzen has already with two matrices, will make a total of 96MB L3 cache.
But we go further, since AMD specifies 1 stack of 3D V-cache for each chiplet, i.e. in the Ryzen 9 we have a certain number of 192 MB in total L3. Most surprisingly of all, AMD itself claims that V-Cache stacks can go up to 8 stacks, also known as 8-hi.
Logically, in the future we would talk about nothing less than 512 MB of L3 plus the cache itself that CCDs have, a real scandal that can boost the performance of any processor to limits we can’t even imagine at the moment.
The current issue for which no more stack is implemented is height. AMD had to reduce the overall height of the CCD and SRAM to maintain the heights the original Ryzen had for it I die.
Die size, heat and unknowns
AMD 3D Chiplet Technology: A Breakthrough in High Performance Computing Packaging.
– AMD (@AMD) June 1, 2021
This is not the first design as such in 3D that we see, but it is the first that is shown in a CPU that is currently on the market as an evolution of it. Doubts are generated and as such, speculation continues to run its course. But in the meantime we have confirmation of the size of AMD’s 3D package: 6x6mm, that is to say an area of 36 mm2 This is what 3D V-Cache technology will occupy in the new Ryzen.
As the SRAM is on top of the CCDs, AMD had to add two silicon brackets on the sides of it, soldered to the dies, which equalizes the height of the assembly and also allows the heat generation of the cores to dies. ‘be optimal and it hardly has any negative effect.
This is possible because unlike the added Cache, the two spring silicones do not include the TSV, while logically the former does. This hybrid approach according to AMD itself makes it possible to increase the density of the interconnects by 200 times and the overall efficiency of the interconnects is improved up to 3 times, so one can imagine the number of pipes that have been created for this purpose.
The improvements are very representative as we see in the demo of the Ryzen 5900X with 3D V-Cache: + 12% on Gears V, an average increase in 15% at stake and a throughput of up to 2TB / s of total internal bandwidth in the processor and its cache, meaning that for the first time in history, the L3 would outperform L1.
It remains to be seen whether AMD will actually introduce these 64 MB of L3 in all models or will include only 32 MB in those that embed a single CCD, where at the same time the question arises whether these new processors already baptized Zen 3+ will arrive at a higher price.
If indeed this 3D V-Cache manages to improve gaming performance by 15% on average, can Intel counteract this effect with Alder Lake-S when it is a completely new architecture and it seems? that it is not focused on the player as such?
For now, we know that from the start we will have these Ryzen, and that the next processors to integrate 3D V-Cache will be the new Milan-X, which should arrive in 2022 to further boost its performance.