In fact, if there is a known ARM design, it is big little, consisting of a heterogeneous architecture made up of larger and more powerful cores to perform demanding tasks and other smaller, low-power cores to save power when the equipment does not require a lot of power. This architecture has been implemented in smartphone chips for a long time and not too long ago Intel (and it even seems AMD with Zen 5) adopted a similar paradigm (but in its own way) in its desktop processors, so everything points to what is the way to go.
ARM DynamIQ, how to increase power without increasing consumption?
The ARM architecture has been working for many years as an alternative to Intel and AMD, but especially in mobile phones and servers thanks to its low consumption, but it was not until Apple decided to create its own M1 chip and l ‘integrate into its computers until that ARM really entered the domestic personal computer industry.
This new architecture that ARM dubbed DynamIQ (it’s an English pun that combines the word “dynamic” with “IQ”, IQ) is primarily aimed at mobile devices and IoT devices, but they have confirmed that they also intend that reached the ecosystem of personal computers and even servers, because its potential is enormous.
According to ARM, the goal of this architecture is to enable its chips to be equipped with virtual reality and machine learning systems, and for that they have added more cores and a greater number of instructions (and c ‘is precisely what ARM still has’ weak’ compared to x86, since its chips have much smaller and more specific instruction sets), offering in total up to 50 times more power in AI tasks.
The underlying theme of DynamIQ is heterogeneous scalability; These two words hide a lot of jargon from the ecosystem, but as ARM predicts that an additional 100 billion ARM chips will be sold in the next 5 years, they point to key areas such as automotive, artificial intelligence and machine learning at the interesting end of that. growth. Therefore, performance, scalability and latency will be key metrics going forward that DynamIQ intends to enable.
A step beyond the big one.
The first step of DynamIQ is a larger cluster paradigm, which means up to eight cores for each of them. However, this means that there can also be a variable kernel design within a cluster; These eight cores could be completely different from each other, and even from different Cortex-A families in different configurations.
The similarity with big.LITTLE is more than obvious, only that instead of having “big kernels” and “small kernels”, here it would directly allow to have a defined number of kernels and that each of them was different from all cores. others (this is really the difference with big.LITTLE).
There are many questions here, such as how the cache hierarchy will allow threads to migrate between cores in a cluster (perhaps the same way threads migrate clústeres big.LITTLE nowadays), even when the cores have different cache layouts. ARM has not yet entered that level of detail, so it is still pending. Each variable-core configuration cluster will be part of a new fabric, with additional power saving modes, and its goal is to provide much lower latency.
The underlying design also allows each core to be independently controlled for voltage and frequency, as well as power saving sleep states. According to the slides provided by ARM, various other IP blocks such as accelerators, should be able to connect to this matrix and benefit from this low latency; items cited by ARM as safety critical automotive decisions could benefit greatly.
One of ARM’s main focus areas is redundancy. The new structure allows a seemingly unlimited number of clusters to be used, so that if one fails, the others can take its place. That said, the type of redundancy that some ARM chip customers might need is failover in the event of physical damage, such as might occur in a self-driving car crash. It will be interesting to see if the vision of ARM with DynamIQ extends to this level of redundancy at the SoC level or if this type of implementation will depend on the ARM partners.
Along with the new framework, ARM said a new memory subsystem design has been implemented to help with compute capabilities; however, nothing specific is mentioned. On the additional compute line, ARM claims that the new dedicated processor instructions (such as limited-precision operations) for HE Yes Machine learning they will be integrated into a variant of the ARMv8 architecture.
We don’t know at this time if this is an extension of ARMv8.2-A that introduced medium precision for data processing, or if it is a brand new version. ARMv8.2-A also adds RAS functionality and memory model improvements, which is consistent with the “new memory subsystem design” mentioned above. ARM said new cores will be needed to make processors with this architecture.
For now, ARM DynamIQ is focusing on new and future technologies such as AI, automotive and mixed reality, although it is true that it is clear that DynamIQ can be used in other models. existing uses such as tablets, smartphones, PCs and servers. It will depend, yes, on how ARM makes it compatible with current base designs, as they could just release it as a separate license.