If you’ve ever wondered why you don’t see Smartphones, tablets and all kinds of x86 processor devices that use less than 10 W and even 5 W. Then tell you that it’s not because of Intel’s lack of interest or AMD, but there are many reasons for this. , a series of insurmountable obstacles related to the design of the X86.
ARM vs x86 o CISC vs RISC
ARM stands for Advanced RISC Machines, while all x-based CPUs are said to have a set similar to CISC commands. But what does this mean? RISC stands for Reduced Instruction Set Computing or Computing with Reduced Instruction Set, while CISC stands for Complex Instruction Set Computing, therefore, it is a method of classifying command sets used by various processors.
The main difference is that because RISC has a reduced set of commands, it is finally necessary to use many simple commands to perform complex, while in the case of CISC unit many complex commands can be simultaneously taught, so CISC drives save space depending on the amount of memory.
For example, the numerical machine code in RISC would be the following:
- Maintains the first operand in the accumulator register
- Upload a second operand and do more.
- Saves the result in the accumulator register.
Instead, in the CISC processor:
- Enter the first and second operand.
With regard to machine code, a RISC track it has many commands therefore it takes more memory, and the CISC binary code is very simple.
Process cycle for processors
Every processor, whether CISC or RISC, must go through four different phases namely:
• Download: The following command is memorized.
• Fix: Instructions are broken down and prepared for execution.
• Release: Instructions are executed by another CPU operating unit. and the effect of the commands is recorded in the corresponding memory bank or register.
In the program RISC Processors CPU commands are equivalent to binary code commands, while in CISC machine code commands can be decay into several small commands, which is change unit performed by CISC processors very difficult and is one of the most important factors for x86 to have high performance.
X86 vs ARM split
One of the differences that all CPUs have since the early 90s is fragmentation, which includes that instead of waiting for a command to be executed entirely in the processor to do the following, this is passed on to each phase of the instruction cycle, which can be divided into several phases each.
Since RISC processors have a direct relationship between the number of binary code commands and those generated by the CPU, it is much easier to separate commands into several categories. However on x86 it is very difficult, as the separation is done in small orders made during the Decode phase, which means more than that additional regionsl running and exercising continuously.
Not only that, but while for example the instructional opcodes for ARMs that do not have a fixed size in x86 format vary, making command naming for smaller commands more complex for x86 processors.
Few records equate to small electrical power
ISA x86 has an inside records are very low than another ISAS, this causes more instructions to be created in the memory, or archives, which causes you to become it ends up consuming a lot of energy during the run. This is an old x86 construction problem not because it is a CISC construction.
To understand it you have to look power consumption of each operation depends on distance between data and processor.
x86 vs ARM on very low power devices.
Intel tried a few years ago with a failed Intel Medfield processor.
In addition, one of the opportunities shown in file creation is CPU mixer, Containing x86 which encloses its commands into ARM commands and allows full compliance between the two ISAS, which can be a clear process.
But sadly ARM or Intel and AMD, especially the latter, have been interested in making this mixed processor since its inception working in both directions can be very difficult to achieve, otherwise the suspension of x86 commands will continue to be a problem, so we will have a processor that can only work in one way and where most circuits will be damaged.