A few months ago the schematic of an AMD patent was leaked, which corresponded to a processor from the AMD Ryzen family, or at least we assume, but with the particularity of showing a fourth level cache in the diagram, something unheard of in AMD processors based on such an architecture.
At the same time, the appearance of Infinity Cache in AMD GPUs raises two questions: are we going to see Infinity Cache implemented in AMD Ryzen processors from AMD, will it be used as L4 cache or some other way?
The utility conflict of Infinity cache and L3 cache of Zen cores
The L3 cache of Zen cores and the Infinity cache of the RDNA 2 architecture perform the same function, as both are victim caches and therefore have the same functionality. This means that when it comes to capturing the data and instructions for each of their corresponding processors, they are in charge of collecting the cache lines rejected by the previous cache level.
What is the problem? To understand this, we have to take into account where the Infinity Cache would go if it were implemented in both SoC and AMD processor, just before the memory controller and therefore in the Northbridge, as the so-called L4 cache.
What is the conflict? It makes no sense that there is a victim cache of another victim cache, because in this case the Infinity cache would be connected to the L3 cache of the Zen cores, which causes a conflict of functions between the two parties.
Infinity Cache connectivity conflicts with Zen cores
If we look at the Infinity Cache of the Navi 21 GPU, we see that there are 16 partitions in total, connected on one end to 16 L2 cache partitions under a 64 byte / cycle bus for each partition and on the other end. 16-channel GDDR6.
The Zen cores of the Ryzen processors are grouped into 4-core (Zen and Zen 2) or 8-core (Zen 3) CCX, but the CCX uses a single Infinity Fabric interface, so the supposed Infinity Cache on a single Zen processor would be made up of a number of partitions at least equal to the number of CCXs.
So in a setup with one CCD you would only have one partition, one with two 2 CCD partitions and the extreme case would be something like an AMD Epyc with 8 CCD which would have 8 partitions. Typically, the size of the caches increases with each additional level and is always twice the sum of the previous cache level.
A single Zen 3 CCD has a capacity of 32MB of L3 cache, a single partition of the Infinity cache is 8MB, a number much lower than it would need to function as an L4 cache of a Zen processor, so in connectivity It is proven that the Infinity cache cannot function like the L4 cache of a processor with CPU Zen.
And what about integrated GPUs?
Since we have seen how the Infinity Cache cannot be used as an additional cache for Zen cores, the only answer left is that Infinity Cache for RDNA 2 cores integrated into SoCs, for the moment AMD has not launched any SoC with an integrated RDNA architecture GPU, due to the launch timing, we don’t expect to see the first generation of RDNA.
In the case of iGPUs, it makes sense to integrate an Infinity Cache located between the memory controller and the GPU, but this would be for the exclusive use of the GPU in the SoC.