With the arrival of the 9 series processors in 2004, Intel wanted to go further in the transmission of different interfaces with the CPU. In the old days you always needed a the north bridge and one Southbridge for the complete communication of any component with the CPU, eliminating one of them was therefore an important step to unify criteria and reduce latencies, as well as to simplify future architectures. This is how DMI was born, which is still in effect today.
A long-term strategy that continues to bear fruit today
With the birth of the new “Core” processors as such and with the i7 990X as a key part of them, Intel has managed to literally destroy AMD in the CPU. Part of the blame for the dominance that the blues impose on the reds comes precisely from the DMI or Direct Media Interface for its acronym in English, and it is nothing more than the link between the processor and its complementary chip, which is usually called PCH
The DMI as such is a data bus which on some occasions and for other buses is developed as an interface, also as a high speed point-to-point link between two chips. Do not confuse DMI with QPI because they are not the same which is important when talking about the second.
DMI made its debut as we said in 2004 hand in hand with the PCH I6 for ix series processors 900, this being the so-called DMI 1.0, which hardly changed anything until the arrival of the second version, much improved.
As they say, DMI 1.0 as such was in effect from 2004 to 2011. The peculiarity of this first version is that it supported both Northbridge and Southbridge, where yes, Intel clearly marked the compatibility and functionality of interface in each case.
This first DMI 1.0 it reached a maximum speed and only in specific cases of 1 Gb / s bidirectional, with the particularity of being able to exercise on up to 4 links at the same time, so we had 4 Gb / s bidirectional in real time.
This version was not touched by Intel until the arrival of DMI 2.0, so it was adapted to each platform in different configurations. But in 2011 and with the so-called new 2.0 version of the bill, Intel doubled the transfer speed to 2 Gb / s with the same lines available and also ended up with the Southbridge as such, and in a way with the Northbridge, leaving a single chip which was now called PCH o Platform Controller Hub, which performed all the functions of both, while others were performed by the processor.
This new version includes a little-known improvement, such as the advanced priority service for recurring traffic with isochronous transfers. This is an enhancement that was intended to maximize QPI performance in multi-socket environments and within mainstream platforms to allow the I / O subsystem by removing northbridge and southbridge to have sufficient of available bandwidth to achieve maximum performance in interfaces such as PCIE, SATA, new generation USB etc.
The last and most current that accompanies us so far, we have the DMI version 3.0, which arrived in 2015 with the Broadwell architecture, itself based on Skylake. The decisive TCPs were those of the 100 series, where it was already allowed to use links with transfers up to 8 GT / s for all four lines and also the speed with the PCH has been increased to almost 4 Gb / s as a direct link.