The chip presented by Intel is, perhaps, one of the greatest achievements of current engineering and at the same time, one of the largest presented in terms of size. Containing two tiles gives it a privilege in terms of cutting edge technology, but if you add everything that has been revealed, you are perhaps faced with the most complex chip ever designed, and much more as a than GPU itself.
Intel Ponte Vecchio GPU: three lithographic processes in the same package
Beyond the fact of including two different matrices and being interconnected as such, which in itself is a big novelty in the world of GPUs. The main thing we have to take into account is that Intel has had at least three different lithographic processes in its new graphics cards.
First of all, we are surprised that the Computing Die will not reach 10nm SuperFin as said, but will arrive with their most recent 7nm, so the density of these will be very high. Second, we have the IO car link manufactured by the current 7nm TSMC, Intel will therefore have inexpensive matrices with a very acceptable logical density and with a good efficiency, unloading its Fabs from said production of an interconnection matrix, which although vital, within of his guild is secondary.
Another of his curiosities is the fact that he found several HBM2 matrices (and not HBM2E as it was supposed), because these matrices have two totally different sizes. It remains to confirm in this regard the batteries that will be integrated, in order to know the total amount of VRAM memory they will have, but rumors point to a minimum of 32 GB.
Passive channels for interconnection and Rambo Caché
The most striking is undoubtedly the passive matrices and the fact that Intel finally integrates its Rambo Caché into the GPU. The former are needed for the interconnection of the tiles, although the frame or internal layers have not been revealed, we know that they do not include any logic inside them beyond the corresponding wiring and the total size of the area they require is surprising.
The Rambo Caché is integrated between the compute dies to minimize latency and will be built by Intel’s current 10nm SuperFin node. There are serious doubts that Intel did not manufacture them at 7nm under EUV, but it is possible that since this is a less complex section than that of IT, Intel chose to choose a process that is already mature and supposedly cheap for the year to come for your creation.
What we know now is that Raja Koduri was not lying when he said that there are 7 advanced technologies in this GPU with 2 tiles:
- Intel 7nm
- TSMC 7 nm
- Foveros 3D packaging
- Improved Super Fin
- Rambo Cache
But at the same time, the rumor also says that this is not the version with the highest capacity and performance from Intel, so we could have a massive chip with higher performance in a short time. In any case, and given the progress of the project, it seems that Intel will meet the deadlines set in its roadmap, both for R&D and for its own development in its Fabs, already entering the more physical part.
Unsurprisingly, if these GPUs were delayed, their Aurora project as the world’s number 1 supercomputer would have to be shut down until the graphics cards for the Ponte Vecchio are ready, which cannot be allowed.