The size of the transistors and the technology they use to make the current path is more important, if not more, than the smaller, more accurate lithographic process, otherwise tell Intel at 14nm. with its developmental effects up to 14 nm ++.
Lithography determines how many transistors can be engraved completely in a square millimeter, but does not specify their electrical benefits. So it's a tandem that each manufacturer has to decide to give consecutive chips to the repair parts.
The length of the gate is crucial to the operation
As we all know, a transistor has a very simple and deterministic function: turn on or off, where two states are assigned in terms of this function: on or off. To accomplish this, the transistor must have a gate at the gate that allows or cut the current flowing through it.
One of these steps is known as the gate length. The shorter length allows greater accuracy in current management and at the same time allows more transistors with mm2, but being too aggressive with this parameter can make performance worse.
Therefore, manufacturers find another way to further optimize transistors, so-called go downThat is, a transistor communication step, something that Intel has taken very seriously with its 14 nm ++ and that has worked up to 10 nm.
But like everything in this industry, it has its limits. According to TSMC, the minimum wavelength is about 25 nm, where you can further reduce the signal the transistor's performance is suffering.
FinFET is coming as Savior, so far
The solution comes from Intel and later other types of technologies that copy the Trigate's advanced concept. With FinFET, each transistor has at least two fins so it will have two control gates, while the Trigate takes the concept further and incorporates the third gate, raising the vertical height of the first two while the third one is the one used by the Superior Power Control and on and turn off.
With this, the passing station has greater control, but other problems arise, such as the small space between the deputies of each lithographic process. Reducing the gates to each lithographic transition means that the space for introducing the fins is smaller and smaller.
This problem comes precisely from the point of view of increasing the pin height and decreasing the width of the gate. If this is not going to continue to dominate the circuits and power supply, only the number of wings will have to be reduced to keep the gates reduced, but this is also impossible because control is lost, so how do manufacturers plan to improve transistors to keep moving?
The solution comes with new round-trip transistors or GAA (Nanosheet)
The limitations allow engineers and companies to explore other options, as they were, in the past that were released due to their extreme complexity.
It is a GAA story called GAA, where these transistors can have wings firmly attached rather than horizontally, what was often called Nanosheet, or nanoblades for their similarity to book sheets or a pack of print sheets.
This type of transistor can save the industry from 5 nm TSMC where from now on the transistors will have alternate layers of silicon and SiGe. The problem is that, as we have already mentioned, its composition is more complex.
To give them life, between the SiGe layers (built between silicon and germanium) it is necessary to have an internal voltage control space and remove it. This spacer will move between the pillar and the gate and consequently specify the width of the gate.
When this is done, the prime minister removes the excess SiGe and by placing the atomic layer on the dielectric gate and exchanging the metal is placed in the proper position between the nanosheet.
If this process is not achieved with sufficient accuracy, the interaction between the remaining silicon and the remaining SiGe can be completely eliminated by starting to deliver very low voltage to the transistor. We talk about the stress of physical stress, because the material is replaced by a series of things to put in place.
The advantage of these nanosheet transistors is that they can resist scalability well below current gates of 25nm, where the limit is unknown but known to be less than 10nm.
In any case, there are several technologies that are being developed, but they all agree that the installation of a virtual repository is the way to go and will make modern transistors completely depleted, allowing for much higher performance in processors and future memories.