Our PC hardware does one thing, transmit electrical signals between its components at different voltages. Depending on the voltage used, the information transmitted has one meaning or another. As new manufacturing nodes were created, new phenomena occurred, but the one that got worse the most was the RC delay.
What is the RC delay?
The RC delay can be translated as the delay of the electrical signal produced by the combination of resistance and capacitance of this part of the circuit. When we talk about resistance, we are talking about the difficulty for electrons to pass through that particular part of the circuit. Capacitance, on the other hand, is the ability of that part of the circuit to store electrical charge.
The RC Delay has become in recent years one of the biggest problems for designers of new chips under new manufacturing nodes. The reason? We normally have the concept that chips are made up of logic gates, which are made up of transistors. The reality is that these logic gates are interconnected with each other by micro-wiring that runs through the circuit and through which the various electrical signals are sent.
So that the signal which separates one logic gate from another is transmitted without there being variations of the electrical signal which could lead to an undesirable variation of the information, it is a question of placing layers of dielectric material between them. cables crossed by the signal. transmitted. The problem is that as the density per zone increases with the new manufacturing nodes, then at the same time the distance between the micro-cabling decreases and therefore the risk of the signal being distorted increases.
Signals and circuits
We tend to understand that any digital integrated circuit works using ones and zeros, which is a simplification of the concept. In reality, it is a question of transmitting information through the internal micro-wiring of the chip under two different voltages where it varies from one to the other continuously.
What is important in a circuit is not only that the signal is transmitted correctly, but that it is transmitted in the correct period. The RC Delay also assumes the speed at which electrons flow through the electrical circuit and therefore influences the final clock speed of the processor.
The problem in the last knots? Although the transistors were scaled within the expected limits, the wiring did not do this to the same degree and they are comparatively larger compared to previous nodes and, therefore, the clock speed does not was not scaled as expected. In other words, it is the interconnection between the various logical components of a processor and its internal memories that led to the end of the MHz race.
The rent rule and its relation to the RC delay
Rent’s rule is linked to the organization of the computational logic within a chip and more precisely to the cabling that interconnects the different logic modules that are part of a processor when it is on the design table. What is the rent rule for? Well, to find out how many interconnects a microprocessor is going to have.
The formula for the Rent rule is as follows:
T = AKp
Where T is the number of terminals and therefore of micro-cables throughout the chip, A is the average number of micro-cables within each logic block and K is the average number of logic gates in each block within the chip . What does this have to do with RC Delay? Well, because the Rent rule allows system architects to know not only the wiring and location of their designs, but also the length of the micro-wiring and therefore the RC delay.
It should also not be forgotten that the distance of the cabling is also related to the power consumption and the longer a cable, the more the data transfer consumption is important, so architects must know how to balance the expected clock speed. and the power consumption of the chip. .
All hope is not lost
The RC delay, although it is an existing problem, is not ignored by the creators of new microprocessors and memories. There are advancements in recent years that have to do with the goal of alleviating the growing problem of RC Delay with newer manufacturing nodes, in particular two types of advancements are being used in parallel:
The first of these is the search for new dielectric materials which allow more efficient isolation of the electrical signal which is distributed from terminal to terminal. So much of the research and development of the new manufacturing nodes to create new CPUs, GPUs and memory is not just about reducing the size of the transistors, but about solving the problems that arise with the new nodes. .
The second lies in the use of vertical structures for the intercommunication of the elements, with which we do not increase the number of terminals, but if the distance between them and therefore we end up reducing the possibilities that the signal of a microcable affects another in the distance between them. The only problem with this approach? For now, we have seen large-scale implementation of the vertical interconnects of memory to memory and even logic to memory, but the future indicates that we will see logic over logic in order to adapt the speed of the process. clock of the different processors.