Tile rendering, the architecture of very low power GPUs

The concept of tile rendering is based on dividing the image buffers into several smaller buffers that we call “tiles”. It is a technique used by GPUs of mobile devices and therefore low power consumption, resulting in significant changes in the internal organization of the graphics processor.

A quick summary of the rasterization pipeline

Tile rendering is a variant of the rasterization algorithm, which is divided into two stages:

• Global space pipeline
• Screen space pipeline

In the World Space Pipeline calculates the geometry of the scene, visualize him as a sculptor making a figure in his studio, at this stage he is not working with pixels but with vertices in a three-dimensional coordinate space.

the Screen Space Pipeline starts with rasterization, which is nothing more than the projection on the plane of the whole 3D scene, imagine for a moment that this same sculptor takes a photo of his work, obviously he has transformed his work into a two-dimensional space, since a photograph is a two-dimensional element.

But our sculptor’s camera is special, it turns out he takes black and white photos, he doesn’t take them in color, so he has to take the photos and edit them on his computer to make them look good. color, which would come to be the texturing process. Finally, the photographer brings the color photo to his printer, which would be equivalent to writing the final pixels into the image buffer.

How is tile rendering different?

Tile rendering has the same steps as traditional rasterization, but adds additional steps to the graphics pipeline, making it a bit slower than traditional rasterization by having a longer pipeline.

Right after finishing the computation of the geometry of the scene, what the GPU does is order the geometry of the scene according to its position on the screen

Yes create a series of new lists of screens, one for each screen thumbnail, In each of them, the geometry information is stored in this part of the screen, said buffer is generated in the VRAM.

The next step is rasterization, but in this case the tiles have just been pixelated one by one, but the advantage is that Each tile’s image buffer is small enough to fit on the GPU’s internal memory, which means that for the operations of the Color buffer and Z buffer do not require VRAM bandwidth, which allows the use of memories with less bandwidth and a considerable reduction in consumption.

In Tile Rendering-based GPUs, we can see more than once the concept “X-core GPU“It’s not actually that there are multiple GPUs on the chip, but rather that it’s designed to process x tiles at the same time during the Screen Space pipeline.

Why is tile rendering not used on desktop GPUs?

The biggest problem with tiled rendering GPUs is the process in which they order the geometry of the scene in the parameter buffer, this process requires more complex hardware the higher the geometric complexity of the scene. AAA games for PC and consoles, where GPUs that are not Tile Renderers are used, have a geometric complexity that prevents Tile Renderers from adapting in this regard as well.

In AMD and NVIDIA GPUs, what exists is tile caching, which is rasterization by tiles but with a series of differences:

• The parameter or triangle buffer is not generated.
• In tile rendering, the pixels of each tile are kept in internal memory until the tile’s screen list is resolved.
• In tile caching, the pixels go to the GPU’s L2 cache so they can switch to VRAM at any time.

At this time, nothing tells us that AMD or NVIDIA will go down the path of tile rendering.