The silicon interposer they have cost concerns, as they are very expensive and require a fairly large amount of silicon, while chip designs using conventional packaging on organic substrates are limited by I / O bandwidth and efficiency energetic. One solution to this problem has been the introduction into the industry of intermediate silicon matrices which connect two logic chips together, but only within a limited range and without using the same footprint as a full silicon interposer. EMIB Intel (Embedded Die Interconnect Bridge) has been the most discussed implementation of this technology in recent times.
TMSC LSI, will this be the future of industry chips?
At TSMC’s 2020 Technology Symposium, the Taiwanese manufacturer detailed its own variant of this technology, called Local Si Interconnect (LSI), which will be offered for InFO and CoWoS encapsulation technologies in the form of InFO-L and CoWoS. -L.
New Advances Are Part Of What TSMC Now Calls Its Packaging Technology 3d fabric, which offers a fairly versatile repertoire of integration and encapsulation options including, of course, SoIC, InFO, and CoWoS.
A brief explanation for our readers who are unfamiliar with these terms: SoIC (Integrated System on Chip) is TSMC’s chip stacking and hybrid link integration technology, which can stack multiple chip bays, which makes the bandwidth extremely high and has a silicon cross link of low consumption. Currently, this technology is unmatched in the industry.
InFO is TSMC’s fan packaging or encapsulation technology, in which a chip is removed from one silicon wafer and placed on another support wafer, on which larger structures such as the RDL are built in copper. (redistribution layer) and then the carrier substrate.
The TSMC variant of InFO with LSI integration is called InFO-L or InFO-LSI, and follows a similar structure with the new addition of this local silicon interconnect intermediate chip for communication between the two chips.
TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) was originally described as the company’s 2.5D silicon interposer conditioning technology, which is currently still under the CoWoS-S specification, but also covers other encapsulation technologies. As its description says, the RDL is built on the base substrate first and it is only in the last step that the silicon chip is added to the set.
CoWoS-L is the new variant of TSMC’s chip packaging technology, adding a silicon local interconnect which is used in combination with a copper RDL to achieve higher bandwidth than using an implementation of RDL packaging. (CoWoS-R), and also has a lower cost than an all-silicon interposer (CoWoS-S). In other words, with this encapsulation technology a better performance at lower cost.
TSMC describes LSI as an active or passive chip (depending on the needs of chip designers and their budget). TSMC Foundry plans to complete InFO-L qualification in the first quarter of 2021, while CoWoS-L is in the prequalification process at the moment. Silicon bridge interconnect technologies such as LSI and EMIB are expected to provide high performance chip designs at lower cost to the designer and the consumer.
In short: better performing and cheaper chips, which should translate (for the user) into more powerful and cheaper processors.