In 2003, one of the most important improvements was made to the importance of processors, the implementation of the Northbridge inside the processor, which until then had been outside of it. The Northbridge is the part that communicates the CPU and other processors on the motherboard with the RAM.
The next step towards integration? If necessary, integrate the RAM or at least part of it inside the CPU.
Distance to data affects performance
One of the basic principles regarding the performance of a processor is the distance between the memory which stores the data and the unit which processes the data, which is the shorter the better due to the fact that the signal electrical has to travel a much shorter distance, which translates into a shorter instruction execution time.
This is why data accessible in the top-level cache will execute faster than data in RAM. The ideal would be to be able to place huge amounts of memory close to the processor.
But it is not possible to do this as space is limited and placing the RAM next to the processor would end up negatively affecting both, causing them together to reach extremely high temperatures which can lead to combined performance. of the two being less than with the two separately.
Using 3DIC technology to integrate RAM into the processor
We have seen 3DIC technology combining multiple stacks of memory chips, but not combining processor with memory, especially in PCs. For example, HBM memory was originally designed to be mounted on a processor, but the temperatures reached were so high that they had to reduce the clock speed of both parties.
In Samsung smartphones, I try to use the Wide I / O standard, which consists of a vertical interface via 512-bit, 200Mhz, SDR-type silicon channels. It only reached 12.8 GB / s but it was offered as an alternative with lower latency and power consumption compared to LPDDR memories of the time. The problem? This increased costs and was therefore rejected by the industry.
The solution has proved elusive, but one of the advantages of a 3DIC system is that it breaks the problem of on-board memory density.
The problem of built-in memory capacity
DRAM has a density 3 times that of SRAM, the problem is that beyond 40nm it is not possible to implement DRAM inside a processor, so the SRAM memory was used. The problem is that SRAM, even at high density, makes it impossible to add enough RAM density to a processor.
The simplest logic tells us that if we put a chip with only RAM on a processor with 3DIC technology, we should increase the density, the problem is that in order to increase the density of memory, we would need a huge memory stack, which would make memory more expensive. processor and would not be viable.
But there is a solution, divide the RAM into two different memory sinks, in a different hierarchy.
Two RAM sinks, one in the processor, the other in the DIMMs
The concept would be that on the one hand we would have a well of RAM memory connected to the processor, with a very low latency and a much faster bandwidth. On the other hand, we would have the classic RAM memory in the classic RAM memory modules of a lifetime.
The idea would be to allocate via the operating system the use of the different RAM sinks of the system, these would not have two memory sinks in sight but only one where the only difference in addressing would be precisely l memory address to which I would write each program.