NEW PCIe 6.0
Although today’s PCs still use PCIe 3.0 and 4.0 connectors, the sixth iteration of this technology has been improving for some time. The fact that the PCIe 6.0 specification is already< /strong> a complete document means that the technology is accurate and functional, so it is only a matter of time until the final version is released and released to the market, according to the following forecast for 2021
PCIe 6.0, is eight times the PCIe of your motherboard
PCIe 6.0 is twice the data transfer rate, which will now be 64 GT / s per pin compared to 32 GT / s for PCIe 5.0 or 16 GT / s for PCIe 4.0. In an effort to increase data transfer speed and bandwidth, the new interface adopted PAM4 (pulse-wide variation with signal level four), which is also used in high-level network technologies such as InfiniBand or GDDR6X graphics memory.
In addition, PCIe 6.0 uses low latency (FEC) error correction to ensure maximum efficiency in data transfer. In general, PCIe 6.0 represents a step forward for this visual interface, but as it introduces a number of technologies, manufacturers will accelerate their development if they want it to reach the market on time (at least “on time” according to their forecast, which was 2021).
The release of version 0.7 of the PCI-Express 6.0 framework is very important because new features can no longer be added after that; this is because the technical details of the technology are already verified using fully functional test chips. In fact, at this stage there are already several companies that may have actual data bus repairs (but not yet announced).
Steps in the specification process
Each type or specification process has a very important meaning, among them five key points:
- Version 0.3: concept. This document explains the global goals of technology and explains how it should be achieved. In PCIe 6.0, direct 64 GT / s bandwidth, the use of PAM4 and FEC is defined.
- Version 0.5: first draft. Here the objectives set out in Figure 0.3 must have been achieved, and the building materials and requirements are also included.
- Version 0.7: complete draft. At this point, where we are at present, the methods and requirements required to achieve the objectives are defined and, in addition, the electrical details must be verified with real chips. At this point, members of the PCI-SIG may suggest the first versions of the following interface.
- Version 0.9: final draft. At this time, internal analysis has already been done on PCI-SIG to improve their copyright. No other changes allowed.
- Version 1.0: presentation. From this version change and development must pass through new literary and engineering innovations (ECNs).
For PCIe 6.0, version 0.5 was published in February of this year, about eight months ago. If all goes according to plan, the new technology will be completed by the second half of 2021, but this does not mean that we will start to see the first products it introduces soon, but that we will have to wait for manufacturers to start using it. on your hardware.
For example, PCI-SIG released version 1.0 of PCI-Express 5.0 at the end of May 2019, but the first platforms to support this technology are Intel and AMD will not enter the market until the end of 2021. By this measure, This means that if PCI-SIG releases version 1.0 of PCI-Express 6.0 by the end of 2021 it means we will see the first batches to install it between 2023 and 2024.